This invention relates to integrated circuits, and more particularly, to integrated circuits with balancing logic that can help to reduce jitter due to power supply voltage variations.
System noise and jitter can adversely affect the performance of modern integrated circuits. Modern circuit designs often require the use of high data rates. Signal timing stability is important for proper device operation, particularly at high data rates. Signal timing stability can be adversely affected by power supply noise. For example, when a number of circuits on an integrated circuit are switched simultaneously, power supply glitches may be produced. These glitches may affect both the positive power supply rail and the power supply ground. The switching speed of digital logic circuits can be affected by the magnitude of the power supply voltage that is used to supply the circuits with power. Circuits generally switch more slowly when they are underpowered than when they are overpowered. Sensitive circuitry that is being powered by power supply signals that contain glitches may therefore experience timing variations (jitter).
Although the impact of power supply noise can sometimes be minimized by switching at slower speeds, this may not be a practical solution for many circuit designs. The use of decoupling capacitors and low-inductance power supply paths may help to reduce the amount of power supply noise in a given integrated circuit, but these techniques are often insufficient to eliminate power supply noise.
It would therefore be desirable to be able to provide improved arrangements for minimizing power supply noise and the resulting signal jitter in integrated circuits.